Electronic phase locked loops have been employed in communications, radar, computers, and other electronic devices for systems since the early 1920's. They were originally employed in direct conversion receivers and televisions to synchronize horizontal and vertical picture sweeps. Today they are used widely in communication systems for frequency synthesis, synchronization of carrier and clock and data recovery, radar systems, clock trees in high speed microprocessors and digital systems tone decoders, video signals, and many other applications. In more recent history, their use has transitioned more into Digital Signal Processing systems in the form of Digital Phase Locked Loops (DPLL).
Frequency generation is an important function performed in both transmitters and receivers for accurate frequency conversion of base band and RF signals. In a transmitter, the frequency synthesizer is often designed to handle low spurious emissions for spectral mask containment and also to maintain proper symbol construction to reduce the error vector magnitude (EVM). For receivers, frequency synthesizers should also exhibit low spurious generation to down convert the desired signal avoiding effects such as reciprocal mixing and to maintain an acceptable signal to noise ratio. Low spurious outputs are also important in carrier and data recovery circuits in which the signal to noise ratio of the recovered carrier is important. Embodiments described herein pertain to a method of controlling spurious outputs in a DPLL.